THE LATCHES
Combinational circuits are characterized by the fact that the output is the logical result of the signals present at the input at the same instant without considering propagation delays. A sequential circuit, on the other hand, also stores the previously assumed states in addition to those currently present at the input . There is a feedback which sends the output signal towards the input . In this type of circuit there is a memorization mechanism of the previous states which condition the following ones. These stored states are called internal variables, and the ability of a sequential circuit to produce its effects using internal variables is due to the delay of the combinatorial circuits in changing output states when a new level is applied to the input.
The delay of signal propagation from input to output is denoted by ∆t. When a signal arrives on the input, this is memorized together with the previous one (still in memory) and brought back to the input. The current data and the one reported in input operate simultaneously producing a new condition in the memory.
LATCH DEFINITION
A latch from the English “grab, hold” is essentially a bistable multivibrator, i.e. a circuit capable of having two stable states, these states are 0 and 1. A latch is therefore capable of maintaining one bit of information, it is implemented with NAND and NOR gates, basically we can say that the RAM of a PC but generally when it comes to storage spaces of digital devices, the memory cells that are a fundamental component of these devices are just latches as they have the ability to block a logical state and keep it over time.
LATCH SR
A Latch SR is the basic element of the sequential logic from which flip-flops are born, i.e. devices that can be synchronized by means of an external signal called clock.
OPERATION
- SET=1, RESET = 0 OUTPUT Q ASSUMES THE VALUE 1 THE LATCH IS SAYING SET.
- SET=0, RESET=1 OUTPUT Q ASSUMES LOGIC LEVEL 0 THE LATCH IS SAID RESET.
- SET=0, RESET=0 THE LOGICAL STATUS OF QE Q̅ DOES NOT SUBJECT TO CHANGES THE LATCH STORES THE PREVIOUS STATUS OF THE OUTPUTS.
- SET=1, RESET=1 VALUES NOT ALLOWED BECAUSE THE OUTPUT CAN ASSUME THE VALUES 0 AND 1 IN DIFFERENTLY.
SR LATCH WITH NOR PORTS
CIRCUIT OPERATION
The SET and RESET buttons are initially inactive and at a potential of 0v thanks to the resistors R1 and R2 thus keeping the last acquired state in memory. Let’s assume that the latch receives a reset pulse turning off the LED on the output of logic gate A since it is at logic level 1. In fact, the R pulse sends the input of the second logic gate B to 1, therefore the output will be 0 which through the feedback brings an input of the NOR A the logic 0, the other input is held at 0V by the resistance R1 therefore the The output of A is at 1 by switching off the led. (First stable state). When the SET button is pressed, the following things happen simultaneously.
- The NOR A input goes to logic level 1 bringing its output to 0 and the LED turns on.
- The low output of NOR A via feedback returns to an input of B which has the other output grounded, therefore the logic level on its output is 1 (second stable state).
GATING
Gating is a technique that allows data to pass from one point of a logic circuit to another, for example between a data input and an output. Let’s see how a circuit based on an AND gate works.
Data will only pass out when a logic level 1 is present at the gate. The gate input is also called Enable, or more simply it is indicated in the integrated circuits with the letter E. The pulse train will go out only when the gate is active.
LATCH WITH ENABLE
We will create a Latch SR with NAND gates, the operation is completely similar to that seen for the NOR gates, therefore we will only consider the new Enable E input.
NAND 1 and 2 enable data to transition to the latch when input E is set to 1. When E is set to 0, the output does not send data to the Latch input, thus keeping the last value left in memory and indicated with x. Operation is analogous to the Latch SR with NOR gates.
D-LATCH
The purpose of the D-Latch is to eliminate the uncertainty condition that occurs when SET and RESET are both at 1. To do this, one of the two inputs must pilot the other.
The data input is indicated with D, it is clear that the NOT gate placed between SET and RESET eliminates the condition of indetermination (if SET=1 RESET=0 and vice versa). The SET and RESET inputs have been merged into D. The D-Latch is particularly suitable for data storage, in fact from the table it can be seen that D passes through the Q output only when the Enable E pin is 1, otherwise the Q data is the one present in a previous qualification. When it is necessary to read the input datum, reading is enabled with E, otherwise the last datum remains in memory. The D-Latch is used in microprocessor systems and in general in the management of data in transit between devices.
THE REGISTER
Combining n D-Latches in cascade real memorization circuits can be formed, the Registers used above all in microprocessor systems where, before being processed, the data of a program are temporarily placed in the registers. Normally programs are written with high-level languages, Java, C++, C# etc. However, when the keywords and program data are executed, they are translated into machine language, ie sequences of bits because the circuitry of computers and electronic devices can only recognize bits.
THE MEMORY
A register is the basic building block of a memory . The size of the memory is defined based on the number of registers used and their width in bits. For example, with 8 D-Latches capable of memorizing a Byte and 16 registers, a 16 Byte memory is created. To access the single registers to read or write the information, a demultiplexer is generally used which takes as input from the address bus the hexadecimal value of the register requested for example by a CPU and directs the output to one of the n registers present. The data and address bus are bidirectional, this to read or write in the various registers.
As regards the address and data bus, the size of the latter depends on the hardware architecture, for example in a 32-bit system it is possible to address 232 memory locations which are more than 4GB. In most modern systems with 64 bit architecture you can address 264 which is a huge amount. If in a multitasking system such as Windows, MacOS and Linux the number of running programs is such as to exhaust the available RAM, then an area of the disk called swap file or virtual memory is used. If you use an SSD disk and you have 16-32GB of RAM or more available, it is better to disable the virtual memory to reduce the number of disk writes and lengthen the life cycle of the SSD.
Leave A Comment