SEQUENTIAL CIRCUITS I FLIP-FLOP

TIMED LOGIC

In wider contexts when digital circuits have to communicate with each other, it is necessary to synchronize the data transfer, also considering the delays that a given circuit can produce. This synchronization or clock is generally obtained by an astable multivibrator which, as we have seen, has no stable state but oscillates by means of RC circuits, producing a square or rectangular wave output. In microprocessors, synchronization is based on quartz circuits, they offer greater stability and much higher working frequencies.

EDGE TRIGGED

So far we have seen how digital circuits are activated by two reference voltages, 0V and 5V. However, in the presence of a clock signal some circuits are activated by the high or low level of the signal, others instead during the transitions of the levels themselves and defined as:

• Positive Edge (Positive Edge Trigged – PET): from level 0 to 1.
• Negative Edge (Negative Edge Trigged – NET): from level 1 to 0.

Depending on the desired edge, it is possible to produce a very short pulse through a characteristic of the TTL family which is the propagation time of a logic gate. But what is meant by propagation time? Basically it is the time interval between the logic level applied at the input and the adjustment at the output. The propagation time of a TTL port is approximately 10ns.

POSITIVE FRONT RECOGNITION

We create a circuit capable of generating a very rapid pulse at the rising edge of the clock.

CIRCUIT OPERATION

The clock signal is applied to the AND gate in two successive moments, directly on the first input and through a NOT gate on the second input. We have seen that the NOT gate generates a propagation delay. In the first half-period of the clock signal indicated in the diagram with (1) the AND gate presents on the first input a logic signal 0 (direct) and on the second input a logic level 1 due to the NOT gate.

POSITIVE FRONT START OF THE CLOCK

When the positive edge of the clock signal begins, indicated by (2), the inputs of the AND gate are both at 1, a high logic level arrives on the first input due to the switching of the clock signal from 0 to 1, while on the other input the delay of the NOT gate of 10 ns causes also the second input pin to be at logic level 1 in place of the switching delay of the NOT gate. This delay kept the output of the AND gate high at the rising edge of the clock.

RECOGNITION NEGATIVE FRONT

In a completely analogous way, the recognition of the negative edge of the clock occurs, replacing the AND gate in the circuit with a NOR gate.

The edge detection circuits are not indicated in the integrated circuits, and are always implied in the clock input.

FLIP-FLOP JK

Similarly to a Latch a flip-flop is able to store a bit, it is therefore a basic element of the memory, but unlike the Latch it can be controlled by a clock signal similar to the Latch enable signal. A generic flip-flop is made by a Latch and a control circuit placed at the input together with the clock signal, both of which perform the timing of the data in transit, for example from J to the output Q.

The inputs J, K are the homologues of the SET, RESET inputs of a Latch, but on the contrary in this circuit there is no uncertainty condition, in fact when J = 1, K = 1 the outputs switch (toggle i.e. invert the state) the positive clock edge arrives. With reference to the diagram drawn above, we can use the following table to summarize the states.

FLIP-FLOP TYPE T

Referring to the previous graph, when the inputs J and K are at level 1 at the output, a logic level inversion occurs. By taking advantage of this feature and connecting J and K together in a new input called T (Toggle) you get a new flip-flop.

By observing the diagram it can be seen that a flip-flop J, K with short-circuited inputs generates at the output a signal having a frequency half of the clock. So for example with a clock of 2MHZ the output would have a frequency of 1MHZ.It is the basic component of the counters, in fact by cascading various T flip-flops to each output, a clock is halved compared to the previous clock.

FLIP-FLOP TYPE D

Input D (Data) is transmitted to output Q only on the rising edge of the clock.At the clock command, it transfers the input to the output and keeps it there until the aforementioned input changes. due to its characteristics it is the basic component of memories (fast) and registers (normal, sliding, ring).

FLIP-FLOP MASTER-SLAVE

The master-slave flip-flop not only uses the rising edge of the clock but both to transmit the data from the input to the output. There is a greater separation between input and output, this allows any circuit connected downstream to process the output data from the slave and at the same time proceed with a new acquisition in the master.

As you can see from the circuit, the separation occurs thanks to a double flip-flop, each one keeps the data during the two transitions of the same. These are called master-slave. Each flip-flop has a control for enabling and synchronization, so that when one is active the other is inactive, achieving the required separation. The NOT gate is of fundamental importance, it times the two flip-flops on the rising and falling edges of the clock, activating and deactivating the respective inputs.

OPERATION

The data is positioned first on the master (rising edge of the clock) then on the slave (falling edge of the clock). From the timing diagram it can be seen that the master-slave flip-flop acquires data on the rising edge of the clock (master) and transfers them to the output of the slave only at the falling edge. A master-slave JK flip-flop can be considered a negative edge trigged since the output data occurs on the falling edge of the clock. Flip-flops in which data passes out through a clock signal are called synchronous, precisely because they are clock-synchronized. However, the need may arise to have a certain level before the clock acts on the circuit, and it is for this reason that the flip-flops are equipped with two asynchronous inputs that force the output to a certain level.

• Pr (Preset) this input when at level 1 it forces the output to high level regardless of the inputs.
• Cr (Clear) When there is a 0 level on Clear, it forces the output to 0.

FLIP-FLOP SYMBOLS

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