ELECTRONIC COUNTERS INTRODUCTION
Electronic counters are made using a chain of flip-flops with NET (Negative Edge Trigged) clock inputs. Based on the number of stages used, the set of outputs for example QA, QB, Qn produces at each clock pulse a binary number equivalent to the number of pulses received. A three-stage counter is called an 8 module as it is able to count from 0 to 7 23 = 8. The binary numbering obtained at the flip-flop output must be interpreted from left to right, that is Qn, QB, QA where the output of the first QA is the least significant bit (LSB) while Qn is the most significant bit (MSB).
4-BIT RIPPLE COUNTER
The 4-BIT RIPPLE electronic counters are made through four JK Negative Edge Trigged flip flops in toggle configuration in which the output of one flip-flop represents the clock input of the next one (Ripple). Since there are 4 modules, the circuit will count 16 pulses from 0 to 15 24 = 16. This is an asynchronous counter as the clock signal is not supplied to all stages at the same time.
OPERATION
- At clock pulse number 9, the value obtained from the 4 outputs is: 1001
- At clock pulse number 15, the value obtained from the 4 outputs is: 1111
This type of flip-flop realizes an up counter and is called UP-COUNTER. It is also possible with this configuration to use the output Q̅ to create a back counter DOWN-COUNTER simply by connecting the output Q̅ to the next clock input.
UP / DOWN ELECTRONIC COUNTERS
In the electronic counters it is possible to exchange the output Q and Q̅ through a circuit to set the count upwards UP or backwards DOWN.
Depending on the switch, the passage of the clock is enabled (direct Q or inverted Q̅). When the switch is open, the AND part at the top is enabled, while the logic level at the inverter output inhibits the lower AND. The reverse situation occurs by enabling the switch. This circuit must be placed between each stage and the switch must act simultaneously on all the inverters present in the exchangers.
SYNCHRONOUS ELECTRONIC COUNTERS
Synchronization consists of supplying the circuit with a clock signal at the same instant. However, if we simultaneously applied a clock signal to an asynchronous counter and not through the outputs, each flip flop would switch at the same instant, not realizing the desired count. In order for a synchronous counter to behave in the desired way, it is necessary to deactivate the flip-flops which must not switch their output according to the expected number, leaving them in the storage state and supplying the inputs J and K with a level 0.
SWITCHING INPUTS J, K
To achieve this, two AND gates are used which sequentially provide the logic state 1 to inputs J and K only when they have to switch the output. The flip-flops are of the master-slave type, the outputs retain the last state acquired before the next clock edge, thus preserving the active AND gates.
OPERATION
Let’s assume that QA AND QB are at level 1, in this situation AND 1 is enabled which in turn enables the third flip-flop (J = K = 1). At the next rising edge, the third flip-flop will also be able to change its state, while QA and QB will not change their state until the falling edge, in which the third flip-flop will also update its output and keep it until the next. enabling. The clock signal in ascending order and in multiples of two controls the two AND gates for enabling the flip-flops. From the binary numbering it can be seen that the third flip-flop must be enabled only for the numbers 4-8-12, while the fourth in correspondence with the number 8. During the counting phase, the two flip-flops that are not enabled reside in the states of storage, therefore their outputs do not change. In phase 2 both AND gates are active so as to produce the number 8. In this situation, the third flip-flop inverts the output from 1 to 0 while the fourth from 0 to 1.
MODULE COUNTER 10
To realize the counter it is necessary to capture the sequence 1010 (10) it is therefore sufficient to connect QB and QD to a NAND gate that resets the counter. In all other combinations (from 0 to 9) the NAND output is at logic level 0, inhibiting the reset of the counter.
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